As integrated circuit fabrication advances from very large scale integration (VLSI) to ultra-large scale integration (ULSI), semiconductor manufacturers continue to develop techniques to construct integrated circuits with structures having dimensions in the sub-micron range on a semiconductor substrate. Improvements in photolithographic processing techniques that can be employed to produce integrated circuits comprising several million transistors per die have substantially contributed to the miniaturization of active semiconductor devices to dimensions below a single micron. The fabrication of these semiconductor devices typically involves the transfer of circuit image patterns from a photolithographic reticle onto a photoresist layer covering a semiconductor wafer substrate using an imaging lens apparatus. The reticle is often itself constructed from a substrate of silicon dioxide and is typically patterned with areas of differing transmissivity thereon, some of these areas being opaque and others being substantially transparent. Collectively, the patterned areas of the reticle represent either the positive or negative images of an integrated circuit structure depending on whether a negative or positive photoresist is utilized. After being properly positioned and aligned over the semiconductor wafer, the reticle is then subjected to electromagnetic radiation, typically in the ultra-violet region of the spectrum. The electromagnetic radiation passes through transparent portions of the reticle, striking portions of the photoresist layer on the wafer. The resist coating is then developed and etched so as to impart a positive or negative image of the reticle pattern onto the photoresist layer remaining on the substrate.
Conventional photolithographic methods of fabricating integrated circuits on a substrate typically involve stepping a reticle and imaging apparatus across a photoresist coated substrate and then repeatedly transferring the reticle image pattern to adjacent areas on the wafer. Each of the individual areas on the wafer containing the circuitry image is termed a die. Typically, the wafer is cut or otherwise segmented at the end of the fabrication process, so that the dies are separated from one another for subsequent packaging as individual integrated circuit chips. The region of the reticle bearing the circuitry image pattern is commonly referred to as a reticle field, and the corresponding patterned region on the die is usually termed the substrate field, or chip field. Depending on the size of the substrate and individual die, a substrate may contain either a few dice or several dozen repetitions of the individual die pattern. The dice are usually arranged uniformly across the substrate in rows and columns. A wafer may undergo several imaging or photolithographic steps, depending on the complexity of the integrated circuit to be formed, with different reticles being employed at different times during the fabrication process to produce individual patterned layers on the die that collectively form the composite integrated circuit structure. This process is generally regarded as being well suited for fabricating integrated circuits having repeating structures such as DRAMs (Dynamic Random Access Memories) and SRAMs (Static Random Access Memories).
As integrated circuits become increasingly complex, however, the integrated circuit structures within an individual die have become significantly smaller and more dense. Larger reticles are often required to transfer larger and more complex circuit images to substrate fields of increased dimensions. Because of inherent image resolution limitations associated with conventional photolithographic processes, imaging and alignment errors are often introduced when fine line structures having sub-micron dimensions are produced on relatively large reticles. Current photolithographic imaging tools, as a consequence, are currently capable of patterning a field with a maximum surface area of only approximately 4.0 cm.sup.2 if fine line structures with dimensions in the sub-micron range are included on the reticle.
Reductions in the dimensions of semiconductor feature sizes are further limited by the size of lenses currently used in photolithographic imaging tools. As features sizes have been reduced, lens sizes have typically increased. Current lenses on average weigh in excess of 450 pounds and cost several million dollars. The large size and high cost of current lenses make further increases in lens sizes highly undesirable. Alternatively, some conventional manufacturing facilities include i-line (Hg) step-and-repeat camera systems for production of semiconductor structures having features of highly reduced dimensions. Unfortunately, typical costs for the i-line systems are in excess of 2.5 million dollars. Deep ultraviolet wavelength (DUV) reflective optics systems available from Silicon Valley Group and DUV refractive systems are also typically regarded as too expensive for incorporation into semiconductor fabrication processes employed by most manufacturers. DUV systems cost approximately 4 million dollars each with an additional cost for investment in appropriate facilities to house the systems.
Thus, there continues to exist in the integrated circuit manufacturing community a need to accommodate highly complex circuitry image patterns of powerful integrated circuits, and to overcome the inherent field size limitations associated with current photolithographic techniques in a cost efficient manner. The present invention fulfills these needs.